The field of the invention relates to semiconductor processing. More particularly, one embodiment relates to a process of making an electrical coupling between semiconductive material and a metal. In particular, an embodiment relates to a process for making a tungsten buried digit line (xe2x80x9cW BDLxe2x80x9d) stack. Another embodiment relates to a source/drain (xe2x80x9cS/Dxe2x80x9d) contact stack.
Semiconductor processing is an intensive activity during which several processes are integrated to achieve a working device. Miniaturization is the process of crowding more semiconductive devices onto a smaller substrate area in order to achieve better device speed, lower energy usage, and better device portability, among others. New processing methods must often be developed to enable miniaturization to be realized. One challenge is to prevent metal or metal silicide agglomeration during back-end-of-line (xe2x80x9cBEOLxe2x80x9d) processing. The challenge to achieve digit line communication in a memory device that has a low resistivity, is often accompanied by the challenge to achieve a temperature-resistant digit line that is protected from the encroachment of damaging elements during BEOL processing, burn-in testing, and field use.
The advent of the buried digit line (xe2x80x9cBDLxe2x80x9d) allowed for a lower overall profile of a dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) device. However, the average grain size (xe2x80x9cgsxe2x80x9d) of a metallization continues to decrease in a manner that causes grains to form that follow the grain boundaries of a substrate. Accordingly, a higher than desirable resistivity persists despite miniaturization.
Another challenge is to fabricate shallow junctions with shallow source/drain (xe2x80x9cS/Dxe2x80x9d) structures that will receive a contact without entirely destroying the shallow S/D structure. Thus, what is needed is a conductive structure that overcomes some of the challenges of the prior art.
The above mentioned problems and challenges are overcome by embodiments of this invention.
One embodiment is directed to a process of forming a tungsten buried digit line (xe2x80x9cWBDLxe2x80x9d) stack on a substrate. The process includes forming a silicon-lean metal silicide first film over a polysilicon plug. Next, an amorphous metal nitride second film is formed by sputtering a metal nitride target above the first film. The amorphous metal nitride second film is covered with a refractory metal third film. A salicidation process causes the first film to form a salicide with the polysilicon plug. Because the buried digit line structures of active devices are formed according to embodiments of the present invention, a lower resistivity and a higher thermal processing yield are achieved.
Another embodiment is directed to a process of forming a source/drain (xe2x80x9cS/Dxe2x80x9d) contact stack structure. The process includes forming a silicon-lean metal silicide first film over a silicon S/D active area. Next, an amorphous metal nitride second film is formed by sputtering a metal nitride target above the first film. The amorphous metal nitride second film is covered with a refractory metal third film. A salicidation process causes the first film to form a salicide with the silicon S/D active area. Because the S/D contact stack structures are formed according to embodiments of the present invention, a lower resistivity and a higher thermal processing yield are achieved.
Another embodiment relates to a device that includes at least one of a BDL structure and a S/D contact stack. The device is packaged and implemented in a host. In one embodiment, the host includes a memory module, In another embodiment, the host includes a computer system with a processor, a memory system, and at least one I/O device connected to the host.